1. Field of the Invention
This invention generally relates to semiconductor devices and the manufacturing method of the same, and more particularly, to field effect semiconductor devices and the manufacturing method of the same. Specifically, the present invention relates to a compound semiconductor device including an enhancement mode FET (hereinafter referred to as E-mode FET) and a depletion mode FET (hereinafter referred to as D-mode FET) and the manufacturing method of the same. In particular, the present invention relates to semiconductor devices mounted on radio frequency (RF) devices that handle several hundreds of MHz or more such as mobile telephones.
2. Description of the Related Art
Conventionally, an E-mode region and a D-mode region are arranged on a single compound semiconductor substrate formed by epitaxial growth. The E-mode FET (Field Effect Transistor) has a normally “off” characteristic and the D-mode transistor has a normally “on” characteristic. That is, the E-mode has a positive threshold voltage Vth at the time a drain current starts flowing. In contrast, the D-mode has a negative threshold voltage. It is possible to downsize radio frequency circuits and improve the characteristics, by fabricating transistors having the above-mentioned different modes on the single compound semiconductor substrate. For example, a switching device can be realized which has, on a single chip, a switch and a logic circuit for controlling the switch. In this case, the E-mode FET may be used in the logic circuit, and the D-mode FET may be used in the switch.
FIG. 1 is a cross-sectional view of a gate electrode and a p-type diffusion layer of the compound semiconductor device described in H. Tosaka, et al., “An antenna Switch MMIC using E/D-mode p-HEMT for GSM/DCS/PCS/WCDMA Bands Application”, 2003 IEEE MTT-S Digest, IFTU-50, pp. 5–8 (hereinafter referred to as Document 1). The compound semiconductor device described in Document 1 is a HEMT (High Electron Mobility Transistor). A gate electrode 14 on the left shown in FIG. 1 is fabricated by evaporating Au/Pt/Ti/Pt on a GaAs layer 12. A p-type diffusion layer 16 on the right is formed by diffusing Pt in the GaAs layer 12 below the gate electrode 14. The E-mode region and the D-mode region are arranged on the same compound semiconductor substrate by controlling a thickness b1 of the p-type diffusion layer.
FIG. 2 is a cross-sectional view of the compound semiconductor device disclosed in Japanese Patent Application Publication No. 5-13464 (hereinafter referred to as Document 2). The compound semiconductor device described in Document 2 is a HEMT. The E-mode region and the D-mode region are arranged on the same compound semiconductor substrate by varying a distance from a Schottky interface of the gate to a channel layer. A compound semiconductor layer 20 is formed on the compound semiconductor substrate by the epitaxial growth. The compound semiconductor layer 20 includes a supply layer 21 of n+-AlGaAs, a channel layer 22 of i-InGaAs, a supply layer 23 of n+-AlGaAs, a barrier layer 24 of i-AlGaAs, a buried layer 25 of i-GaAs, an etching stopper layer 26 of n+-AlGaAs, and a cap layer 27 of n+-GaAs. Gate electrodes 28 and 29 have recess structures and are embedded in compound semiconductor layers 24 and 25. A distance D1 is shorter than a distance D2 (D1<D2). The distance D1 is from the Schottky interface of the gate electrode 28 in an E-type transistor to the channel layer 22. The distance D2 is from the Schottky interface of the gate electrode 29 in the D-mode region to the channel layer 22.
The conventional techniques shown in FIGS. 1 and 2, however, have the following drawbacks.
The conventional technique shown in FIG. 1 has a drawback in controlling the threshold voltage Vth(E) of the E-mode transistor. This threshold voltage Vth(E) varies according to the thickness b1 of the p-type diffusion layer 16. However, the p-type impurities such as Pt or Zn have large diffusion coefficients. Therefore, the thickness b1 varies according to the thermal history in the fabrication process. It is extremely difficult to control the threshold voltage Vth(E) at a constant value due to the variation of the thickness b1. The thickness b1 of the p-type diffusion layer 16 also varies according to the thickness a1 of the evaporated Pt film that forms the lowermost layer of the gate electrode 15. According to Document 1, a slight variation of the evaporated film thickness a1 causes a wide variation of the threshold voltage Vth(E). The controllability of the threshold value Vth(E) is not sufficient. Therefore, it is difficult to separately fabricate transistors having a Vth(D) of −0.2 V and a Vth(E) of +0.2 V on the single compound semiconductor substrate in which Vth(D) is small and the difference between Vth(D) and Vth(E) is also small.
It is necessary to make the distance D1 thin in order to achieve the E-mode with the conventional technique shown in FIG. 2. The distance D1 corresponds to the sum of the thickness of the barrier layer 24 and that of the supply layer 23. However, if the distance D1 becomes smaller than a certain value, the forward Schottky diode characteristics of the gate electrode 28 are drastically degraded. FIG. 3 shows the above-mentioned drawback. The horizontal axis in FIG. 3 denotes the thickness of the barrier layer 24, and one vertical axis on the left denotes the threshold value Vth[V] of the E-mode FET. The other vertical axis on the right denotes a forward voltage drop Vf[V]. A gate length Lg of the gate electrode 28 is equal to 0.4 μm. As seen in experiment results in FIG. 3, as the barrier layer 24 becomes thinner, the threshold voltage becomes greater and the E-mode can be achieved. However, in the case where the thickness of the barrier layer 24 is nine nanometers or less, the forward voltage drop Vf drastically drops. If the supply layer 23 requires 11 nanometers in thickness in order to hold the D-mode characteristics, the E-mode having the Vth of 0.2 V cannot be achieved without setting the barrier layer 24 to be six nanometers in thickness. In fact, excellent forward Schottky diode characteristics cannot be obtained with the barrier layer 24 of six nanometers. Besides, there is another drawback in that it is difficult to control the thickness of the barrier layer 24 accurately with etching.